1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to technologies for configuring a variable unit delay circuit and a clock generation circuit of a semiconductor apparatus.
2. Related Art
A semiconductor apparatus typically operates in synchronization with a periodic reference pulse signal such as a clock so as to improve an operational speed and ensure efficient internal operation. In fact, most semiconductor apparatuses operate using clock signals supplied from outside or internal clocks generated inside as needed by the circumstances.
A clock generation circuit such as a delay locked loop (DLL) is provided in order to compensate for a timing difference between an external clock signal and an internal clock signal. Such clock generation circuit comprises a plurality of unit delay cells therein so as to generate an output clock signal. In general, increase in the number of unit delay cells disadvantageously affects an area and current consumption. Therefore, a technology capable of minimizing the unit delay cell is necessary in the art.